1. Filed of the Invention
The present invention relates to latch circuits, and in particular, to low power latch circuits with reduced signal leakage.
2. Description of the Related Art
With its advantage of low power consumption, logic circuitry with complementary metal oxide semiconductor field effect transistors (C-MOSFETs) has seen ever increasing use in recent years. As MOSFET technology has evolved, individual MOSFETs have become steadily smaller, e.g. with smaller feature sizes, particularly shorter channel lengths. This has allowed more and more MOSFETs to be integrated together in one integrated circuit (IC), as well as allow the requisite power supply voltage (VDD) to be lowered as well. Benefits of the former include reduced size and increased operating frequencies, while benefits of the latter include reduced power consumption. However, operating MOSFETs at today's lower power supply voltages has the undesirable effect of lowering MOSFET current which reduces the maximum operating frequency. Hence, in order to minimize reductions in circuit performance, the MOSFET threshold voltages (V.sub.TH) are reduced so as to minimize reductions in the MOSFET current. (Further discussion of the relationship(s) between power supply voltage, threshold voltage and operating performance for MOSFETs can be found in commonly assigned, copending U.S. patent application Ser. No. 08/292,513, filed Aug. 18, 1994, and entitled "Low Power, High Performance Junction Transistor", the disclosure of which is hereby incorporated herein by reference.) However, this in turn has the undesired effect of increasing MOSFET leakage current, i.e. MOSFET current flowing when the device is turned off. This results in charge leakage to and from the signal nodes of each logic cell which prevents signal levels from achieving and maintaining full VDD and VSS values, thereby decreasing noise immunity and increasing chances of failure due to data losses caused by such leakage to or from the signal nodes. Additionally, in static logic circuits, this can result in leakage currents flowing to or from the signal nodes of each logic cell, thereby increasing the current requirements for the power supply(ies).
Accordingly, it would be desirable to have a logic circuit having transistors with reduced threshold voltages so as to take maximum advantage of the benefits available from the use of lower power supply voltages while simultaneously minimizing chances of failure due to data losses caused by signal leakage to or from data storage nodes, minimizing reductions in maximum operating frequency and providing improved output signal levels for improved noise immunity, as well as minimizing power supply current requirements.